FISH
A Forth engine for ASIC embedding

R. J. Brown -- rj@eli.wariat.org
Elijah Laboratories Inc. (847) 705-0370
759 Independence Dr. #5, Palatine IL 60074

Abstract:

FISH is a reaction to the scarcity of good embeddable CPU designs. FISH was designed at the block diagram level between 11:00 AM and 1:00 PM Saturday, February 10, 1996, as a joint effort between myself and Jeff Frederickson of Frederickson Laboratories Inc. The need for FISH was created by the design of a single chip decoder for MPEG-2 video and audio for the mutual client of both Frederickson Labs and Elijah Labs, Audio Digital Imaging Inc. ADI is developing the Apogee-2 MPEG-2 decoder chip, and needed a CPU core to control it. It was desired to have the CPU design implemented in Verilog at both the behavioural and synthesizable levels so the the overall chip design could be simulated on workstations, and also manufactured at potentially multiple foundries.