While several foundries claimed to have CPU cores, none were portable between foundries, and documentation on them all (MIPS and ARM) was incomplete when we needed details to develop software and hardware interfaces. Rather than hold up the project waiting for details, we started looking for alternative CPU cores. Several Forth stack machine designs were already developed, but none in Verilog. A MIPS core was located, but the price was prohibitive, and it has never actually been put into silicon before.
The only Verilog design that was affordable was a 286 clone, but the Verilog was output by an automatic translation back-end to a proprietary design tool, and was therefore more like object code than source code. It would have been hard to optimize to different vendors processes, and very slow in simulation.
Because of these difficulties, it was decided to try and develop a CPU core written in Verilog, with a C++ object oriented model as the first step.